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W39V040FA 512K x 8 CMOS FLASH MEMORY WITH FWH INTERFACE
1. GENERAL DESCRIPTION
The W39V040FA is a 4-megabit, 3.3-volt only CMOS flash memory organized as 512K x 8 bits. For flexible erase capability, the 4Mbits of data are divided into 8 uniform sectors of 64 Kbytes, which are composed of 16 smaller even pages with 4 Kbytes. The device can be programmed and erased insystem with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture of the W39V040FA results in fast program/erase operations with extremely low current consumption. This device can operate at two modes, Programmer bus interface mode and FWH bus interface mode. As in the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. But in the FWH interface mode, this device complies with the Intel FWH specification. The device can also be programmed and erased using standard EPROM programmers.
2. FEATURES
* Single 3.3-volt operations: * Hardware protection:
- 3.3-volt read - 3.3-volt erase - 3.3-volt program
* Fast Program operation:
- Optional 16K byte or 64K byte Top Boot Block with lockout protection - #TBL & #WP support the whole chip hardware protection
* Flexible 4K-page size can be used as
- Byte-by-Byte programming: 35 S (typ.)
* Fast erase operation:
Parameter Blocks
* Low power consumption
- Chip erase 100 mS (max.) - Sector erase 25 mS (max.) - Page erase 25 mS (max.)
* Fast Read access time: Tkq 11 nS * Endurance: 10K cycles (typ.) * Twenty-year data retention * 8 Even sectors with 64K bytes each, which is
- Active current: 12.5 mA (typ. for FWH mode)
* Automatic program and erase timing with
internal VPP generation
* End of program or erase detection
- Toggle bit - Data polling
* Latched address and data * TTL compatible I/O * Available packages: 32L PLCC, 32L STSOP,
composed of 16 flexible pages with 4K bytes
* Any individual sector or page can be erased
40L TSOP (10 x 20 mm)
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Publication Release Date: December 19, 2002 Revision A2
W39V040FA
3. PIN CONFIGURATIONS 4. BLOCK DIAGRAM
A 8 ^ F G P I 2 v 4 A7(FGPI1) A6(FGPI0) A5(#WP) A4(#TBL) A3(ID3) A2(ID2) A1(ID1) A0(ID0) DQ0(FWH0) 5 6 7 8 9 10 11 12 13
A 9 ^ F G P I 3 v 3
# R E S V END TCD 2
R / # C ^ C L K v
A 1 0 ^ F G P I 4 v
#WP #TBL CLK FWH[3:0] FWH4 IC #INIT #RESET
7FFFF FWH Interface BOOT BLOCK 64K BYTES MAIN MEMORY BLOCK6 64K BYTES MAIN MEMORY BLOCK5 64K BYTES MAIN MEMORY BLOCK4 64K BYTES MAIN MEMORY BLOCK3 64K BYTES Programmer Interface MAIN MEMORY BLOCK2 64K BYTES MAIN MEMORY BLOCK1 64K BYTES MAIN MEMORY BLOCK0 64K BYTES 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 3FFFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 00000 Optional 16KBytes as Boot Block 4K Page 4K Page 4K Page 4K Page 4K Page 4K Page 4K Page 4K Page 4K Page 4K Page 4K Page 4K Page
7FFFF
7C000 7BFFF
1 32 31 30 29 28 27 26 IC
R/#C A[10:0] DQ[7:0] #OE #WE
VSS
NC NC
32L PLCC
25 24 23 22 21
VDD
#OE(#INIT) #WE(FWH4)
NC
DQ7(RSV)
70000
14 15 16 17 18 19 20 D Q 1 ^ F W H 1 v DVDD QSQQ 2S34 ^ ^^ F FR W WS H HV 2 3v v v D Q 5 ^ R S V v D Q 6 ^ R S V v
5. PIN DESCRIPTION
SYM. INTERFACE PGM * * FWH * * * * * * * * * * * * * * * * * * * * * * * Reset Initialize Top Boot Block Lock Write Protect CLK Input General Purpose Inputs Identification Inputs They Are Internal Pull Down to Vss Address/Data Inputs FWH Cycle Initial Row/Column Select Address Inputs Data Inputs/Outputs Output Enable Write Enable Power Supply Ground Reserved Pins No Connection PIN NAME Interface Mode Selection
NC NC NC VSS IC A10(FGPI4) R/#C(CLK) VDD NC #RESET A9(FGPI3) A8(FGPI2) A7(FGPI1) A6(FGPI0) A5(#WP) A4(#TBL)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32L STSOP
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
#OE(#INIT) #WE(FWH4) V DD DQ7(RSV) DQ6(RSV) DQ5(RSV) DQ4(RSV) DQ3(FWH3) VSS DQ2(FWH2) DQ1(FWH1) DQ0(FWH0) A0(ID0) A1(ID1) A2(ID2) A3(ID3)
IC #RESET #INIT #TBL #WP CLK FGPI[4:0]
NC IC NC NC NC NC A10(FGPI4) NC CLK VDD NC #RESET NC NC A9(FGPI3) A8(FGPI2) A7(FGPI1) A6(FGPI0) A5(#WP) A4(#TBL)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VSS VDD
ID[3:0] FWH[3:0] FWH4 R/#C A[10:0] DQ[7:0] #OE #WE VDD VSS RSV NC
#WE(FWH4) #OE(#INIT) NC
DQ7(RSV) DQ6(RSV) DQ5(RSV) DQ4(RSV) VDD VSS VSS
40L TSOP
DQ3(FWH3) DQ2(FWH2) DQ1(FWH1) DQ0(FWH0) A0(ID0) A1(ID1) A2(ID2) A3(ID3)
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W39V040FA
6. FUNCTIONAL DESCRIPTION
Interface Mode Selection and Description
This device can operate in two interface modes, one is Programmer interface mode, and the other is FWH interface mode. The IC pin of the device provides the control between these two interface modes. These interface modes need to be configured before power up or return from #RESET. When IC pin is set to high state, the device will be in the Programmer mode; while the IC pin is set to low state (or leaved no connection), it will be in the FWH mode. In Programmer mode, this device just behaves like traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed. The row address are mapped to the higher internal address A[18:11]. And the column address are mapped to the lower internal address A[10:0]. For FWH mode, it complies with the FWH Interface Specification. Through the FWH[3:0] and FWH4 to communicate with the system chipset .
Read (Write) Mode
In Programmer interface mode, the read (write) operation of the W39V040FA is controlled by #OE (#WE). The #OE (#WE) is held low for the host to obtain (write) data from (to) the outputs (inputs). #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when #OE is high. As for in the FWH interface mode, the read or write is determined by the "bit 0 & bit 1 of START CYCLE ". Refer to the FWH cycle definition and timing waveforms for further details.
Reset Operation
The #RESET input pin can be used in some application. When #RESET pin is at high state, the device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read or standby mode, it depends on the control signals.
Boot Block Operation and Hardware Protection at Initial- #TBL & #WP
There are two alternatives to set the boot block. Either 16K-byte or 64K-byte in the top location of this device can be locked as boot block, which can be used to store boot codes. It is located in the last 16K/64K bytes of the memory with the address range from 7C000(hex)/70000(hex) to 7FFFF(hex). See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout), other memory locations can be changed by the regular programming method. Besides the software method, there is a hardware method to protect the top boot block and other sectors. Before power on programmer, tie the #TBL pin to low state and then the top boot block will not be programmed/erased. If #WP pin is tied to low state before power on, the other sectors will not be programmed/erased. In order to detect whether the boot block feature is set on or not, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address 7FFF2(hex). If the DQ0/DQ1 output data is "1," the 64Kbytes/16Kbytes boot block programming lockout feature will be activated; if the DQ0/DQ1 output data is "0," the lockout feature will be inactivated and the boot block can be erased/programmed. But the hardware protection will override the software lock setting, i.e., while the #TBL pin is trapped at low state, the top boot block cannot be Publication Release Date: December 19, 2002 Revision A2
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W39V040FA
programmed/erased whether the output data, DQ0/DQ1 at the address 7FFF2, is "0" or "1". The #TBL will lock the whole 64Kbytes top boot block, it will not partially lock the 16Kbytes boot block. You can check the DQ2/DQ3 at the address 7FFF2 to see whether the #TBL/#WP pin is in low or high state. If the DQ2 is "0", it means the #TBL pin is tied to high state. In such condition, whether boot block can be programmed/erased or not will depend on software setting. On the other hand, if the DQ2 is "1", it means the #TBL pin is tied to low state, then boot block is locked no matter how the software is set. Like the DQ2, the DQ3 inversely mirrors the #WP state. If the DQ3 is "0", it means the #WP pin is in high state, then all the sectors except the boot block can be programmed/erased. On the other hand, if the DQ3 is "1", then all the sectors except the boot block are programmed/erased inhibited. To return to normal operation, perform a three-byte command sequence (or an alternate single-byte command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.
Chip Erase Operation
The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycle, the device enters the internal chip erase mode, which is automatically timed and will be completed within fast 100 mS (max). The host system is not required to provide any control or timing during this operation. If the boot block programming lockout is activated, only the data in the other memory sectors will be erased to FF(hex) while the data in the boot block will not be erased (remains as the same state before the chip erase operation). The entire memory array will be erased to FF(hex) by the chip erase operation if the boot block programming lockout feature is not activated. The device will automatically return to normal read mode after the erase operation completed. Data polling and/or Toggle Bits can be used to detect end of erase cycle.
Sector/Page Erase Command
Sector/page erase is a six bus cycles operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles then follows by the sector/page erase command. The sector/page address (any address location within the desired sector/page) is latched on the falling edge of #WE, while the command (30H/50H) is latched on the rising edge of #WE. Sector/page erase does not require the user to program the device prior to erase. When erasing a sector/page or sectors/pages the remaining unselected sectors/pages are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector/page erase begins after the erase command is completed, right from the rising edge of the #WE pulse for the last sector/page erase command pulse and terminates when the data on DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an address within any of the sectors/pages being erased. Refer to the Erase Command flow Chart using typical command strings and bus operations.
Program Operation
The W39V040FA is programmed on a byte-by-byte basis. Program operation can only change logical data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot block from "0" to "1", is needed before programming. The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte Programming). The device will internally enter the program operation immediately after the byteprogram command is entered. The internal program timer will automatically time-out (50 S max. TBP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle. -4-
W39V040FA
Hardware Data Protection
The integrity of the data stored in the W39V040FA is also hardware protected in the following ways: (1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle. (2) VDD Power Up/Down Detection: The programming and read operation are inhibited when VDD is less than 1.5V typical. (3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods. (4) VDD power-on delay: When VDD has reached its sense level, the device will automatically time-out 5 mS before any write (erase/program) operation.
Data Polling (DQ7)- Write Status Detection
The W39V040FA includes a data polling feature to indicate the end of a program or erase cycle. When the W39V040FA is in the internal program or erase cycle, any attempts to read DQ7 of the last byte loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ7 will show the true data. Note that DQ7 will show logical "0" during the erase cycle, and when erase cycle has been completed it becomes logical "1" or true data.
Toggle Bit (DQ6)- Write Status Detection
In addition to data polling, the W39V040FA provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation.
Register
There are three kinds of registers on this device, the General Purpose Input Registers, the Block Lock Control Registers and Product Identification Registers. Users can access these registers through respective address in the 4Gbytes memory map. There are detail descriptions in the sections below.
General Purpose Inputs Register
This register reads the FGPI[4:0] pins on the W39V040FA.This is a pass-through register which can read via memory address FFBC0100(hex). Since it is pass-through register, there is no default value. GPI Register Table BIT 7-5 4 3 2 1 0 Reserved Read FGPI4 pin status Read FGPI3 pin status Read FGPI2 pin status Read FGPI1 pin status Read FGPI0 pin status FUNCTION
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Publication Release Date: December 19, 2002 Revision A2
W39V040FA
Block Locking Registers
This part provides 8 even 64Kbytes blocks, and each block can be locked by register control. These control registers can be set or clear through memory address. Below is the detail description. Block Locking Registers type and access memory map Table
REGISTERS BLR7 BLR6 BLR5 BLR4 BLR3 BLR2 BLR1 BLR0 REGISTERS TYPE R/W R/W R/W R/W R/W R/W R/W R/W CONTROL BLOCK 7 6 5 4 3 2 1 0 DEVICE PHYSICAL ADDRESS 7FFFFh - 70000h 6FFFFh - 60000h 5FFFFh - 50000h 4FFFFh - 40000h 3FFFFh - 30000h 2FFFFh - 20000h 1FFFFh - 10000h 0FFFFh - 00000h 4GBYTES SYSTEM MEMORY ADDRESS FFBF0002h FFBE0002h FFBD0002h FFBC0002h FFBB0002h FFBA0002h FFB90002h FFB80002h
Block Locking Register Bits Function Table
BIT FUNCTION
7-3 2
1
0
Reserved Read Lock 1: Prohibit to read in the block where set 0: Normal read operation in the block where clear. This is default state. Lock Down 1: Prohibit further to set or clear the Read Lock or Write Lock bits. This Lock Down Bit can only be set not clear. Only the device is reset or re-powered, the Lock Down Bit is cleared. 0: Normal operation for Read Lock or Write Lock. This is the default state. Write Lock 1: Prohibited to write in the block where set. This is default state. 0: Normal programming/erase operation in the block where clear.
Register Based Block Locking Value Definitions Table
BIT [7:3] 00000 00000 00000 00000 00000 00000 00000 00000 BIT 2 0 0 0 0 1 1 1 1 BIT 1 0 0 1 1 0 0 1 1 BIT 0 0 1 0 1 0 1 0 1 Full Access. Write Lock. Default State. Locked Open (Full Access, Lock Down). Write Locked, Locked Down. Read Locked. Read & Write Locked. Read Locked, Locked Down. Read & Write Locked, Locked Down. RESULT
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W39V040FA
Read Lock
Any attempt to read the data of read locked block will result in "00." The default state of any block is unlocked upon power up. User can clear or set the write lock bit anytime as long as the lock down bit is not set.
Write Lock
This is the default state of blocks upon power up. Before any program or erase to the specified block, user should clear the write lock bit first. User can clear or set the write lock bit anytime as long as the lock down bit is not set. The write lock function is in conjunction with the hardware protect pins, #WP & TBL. When hardware protect pins are enabled, it will override the register block locking functions and write lock the blocks no matter how the status of the register bits. Reading the register bit will not reflect the status of the #WP or #TBL pins.
Lock Down
The default state of lock down bit for any block is unlocked. This bit can be set only once; any further attempt to set or clear is ignored. Only the reset from #RESET or #INIT can clear the lock down bit. Once the lock down bit is set for a block, then the write lock bit & read lock bit of that block will not be set or cleared, and keep its current state.
Product Identification Registers
In the FWH interface mode, a read from FFBC, 0000(hex) can output the manufacturer code, DA(hex). A read from FFBC, 0001(hex) can output the device code 34(hex). There is an alternative software method (six commands bytes) to read out the Product Identification in both the Programmer interface mode and the FWH interface mode. Thus, the programming equipment can automatically matches the device with its proper erase and programming algorithms. In the software access mode, a six-byte (or JEDEC 3-byte) command sequence can be used to access the product ID for programmer interface mode. A read from address 0000(hex) outputs the manufacturer code, DA(hex). A read from address 0001(hex) outputs the device code, 34(hex)." The product ID operation can be terminated by a three-byte command sequence or an alternate one-byte command sequence (see Command Definition table for detail).
Table of Operating Mode
Operating Mode Selection - Programmer Mode
MODE PINS
#OE VIL VIH X VIL X VIH
#WE VIH VIL X X VIH X
#RESET VIH VIH VIL VIH VIH VIH
ADDRESS
DQ.
Read Write Standby Write Inhibit Output Disable
AIN AIN X X X X
Dout Din High Z High Z/DOUT High Z/DOUT High Z
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Publication Release Date: December 19, 2002 Revision A2
W39V040FA
Operating Mode Selection - FWH Mode
Operation modes in FWH interface mode are determined by "START Cycle" when it is selected. When it is not selected, its outputs (FWH[3:0]) will be disable. Please reference to the "FWH Cycle Definition".
Table of Command Definition
COMMAND DESCRIPTION Read Chip Erase Sector Erase Page Erase Byte Program Top Boot Block Lockout - 64K/16KByte Product ID Entry Product ID Exit Product ID Exit
(4) (4)
NO. OF Cycles (1) 1 6 6 6 4 6 3 3 1
1ST CYCLE Addr. Data AIN DOUT 5555 AA 5555 AA 5555 AA 5555 AA 5555 AA 5555 AA 5555 AA XXXX F0
2ND CYCLE Addr. Data 2AAA 55 2AAA 55 2AAA 55 2AAA 55 2AAA 55 2AAA 55 2AAA 55
3RD CYCLE Addr. Data 5555 80 5555 80 5555 80 5555 A0 5555 80 5555 90 5555 F0
4TH CYCLE Addr. Data 5555 AA 5555 AA 5555 AA AIN DIN
5TH CYCLE Addr. Data 2AAA 55 2AAA 55 2AAA 55
6TH CYCLE Addr. Data 5555 10 SA (5) 30 PA (6) 50
5555 AA
2AAA 55
5555 40/70
Notes: 1. The cycle means the write command cycle not the FWH clock cycle. 2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[18:11] 3. Address Format: A14-A0 (Hex); Data Format: DQ7-DQ0 (Hex) 4. Either one of the two Product ID Exit commands can be used. 5. SA: Sector Address SA = 7XXXXh for Unique Sector7 (Boot Sector) SA = 6XXXXh for Unique Sector6 SA = 5XXXXh for Unique Sector5 SA = 4XXXXh for Unique Sector4 6. PA : Page Address PA = 7FXXXh for Page 15 in Sector 7 PA = PA = 7EXXXh for Page 14 in Sector 7 6FXXXh to PA = 7DXXXh for Page 13 in Sector 7 PA = 7CXXXh for Page 12 in Sector 7 60XXXh for PA = 7BXXXh for Page 11 in Sector 7 Page 15 PA = 7AXXXh for Page 10 in Sector 7 to PA = 79XXXh for Page 9 in Sector 7 Page 0 PA = 78XXXh for Page 8 in Sector 7 In PA = 77XXXh for Page 7 in Sector 7 Sector 6 PA = 76XXXh for Page 6 in Sector 7 (Reference to the PA = 75XXXh for Page 5 in Sector 7 first PA = 74XXXh for Page 4 in Sector 7 column) PA = 73XXXh for Page 3 in Sector 7 PA = 72XXXh for Page 2 in Sector 7 PA = 71XXXh for Page 1 in Sector 7 PA = 70XXXh for Page 0 in Sector 7 PA = 5FXXXh to 50XXXh for Page 15 to Page 0 In Sector 5 (Reference to the first column) PA = 4FXXXh to 40XXXh for Page 15 to Page 0 In Sector 4 (Reference to the first column) PA = 3FXXXh to 30XXXh for Page 15 to Page 0 In Sector 3 (Reference to the first column) PA = 2FXXXh to 20XXXh for Page 15 to Page 0 In Sector 2 (Reference to the first column) PA = 1FXXXh to 10XXXh for Page 15 to Page 0 In Sector 1 (Reference to the first column) PA = 0FXXXh to 00XXXh for Page 15 to Page 0 In Sector 0 (Reference to the first column) SA = 3XXXXh for Unique Sector3 SA = 2XXXXh for Unique Sector2 SA = 1XXXXh for Unique Sector1 SA = 0XXXXh for Unique Sector0
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W39V040FA
FWH Cycle Definition
FIELD START IDSEL MSIZE TAR ADDR NO. OF CLOCKS 1 1 1 2 7 DESCRIPTION "1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH Memory Write cycle. 0000b" appears on FWH bus to indicate the initial This one clock field indicates which FWH component is being selected. Memory Size. There is always show "0000b" for single byte access. Turned Around Time Address Phase for Memory Cycle. FWH supports the 28 bits address protocol. The addresses transfer most significant nibble first and least significant nibble last. (i.e. Address[27:24] on FWH[3:0] first, and Address[3:0] on FWH[3:0] last.) Synchronous to add wait state. "0000b" means Ready, "0101b" means Short Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" means error, and other values are reserved. Data Phase for Memory Cycle. The data transfer least significant nibble first and most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first, then DQ[7:4] on FWH[3:0] last.)
SYNC
N
DATA
2
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Publication Release Date: December 19, 2002 Revision A2
W39V040FA
Embedded Programming Algorithm
Start
Write Program Command Sequence (see below)
#Data Polling/ Toggle bit
Pause T BP
No Increment Address Last Address ? Yes Programming Completed
Program Command Sequence (Address/Command):
5555H/AAH
2AAAH/55H
5555H/A0H
Program Address/Program Data
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W39V040FA
Embedded Erase Algorithm
Start
Write Erase Command Sequence (see below)
#Data Polling or Toggle Bit Successfully Completed
Pause T EC /TSEC/TPEC
Erasure Completed
Chip Erase Command Sequence (Address/Command): 5555H/AAH
Individual Sector Erase Command Sequence (Address/Command): 5555H/AAH
Individual Page Erase Command Sequence (Address/Command): 5555H/AAH
2AAAH/55H
2AAAH/55H
2AAAH/55H
5555H/80H
5555H/80H
5555H/80H
5555H/AAH
5555H/AAH
5555H/AAH
2AAAH/55H
2AAAH/55H
2AAAH/55H
5555H/10H
Sector Address/30H
Page Address/50H
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Publication Release Date: December 19, 2002 Revision A2
W39V040FA
Embedded #Data Polling Algorithm
Start
VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase operation = Any of the page addresses within the page being erased during page erase operation = Any of the device addresses being erased during chip erase operation
Read Byte (DQ0 - DQ7) Address = VA
No
DQ7 = Data ? Yes Pass
Embedded Toggle Bit Algorithm
Start
Read Byte (DQ0 - DQ7) Address = Don't Care
Yes
DQ6 = Toggle ? No Pass
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W39V040FA
Software Product Identification and Boot Block Lockout Detection Acquisition Flow
Product Identification Entry (1)
Load data AA to address 5555
Identification and Boot Block Lockout Detection Mode (3)
Product
Product Identification Exit(6)
Load data AA to address 5555 (2)
Load data 55 to address 2AAA
Read address = 00000 data = DA
Load data 55 to address 2AAA
Load data 90 to address 5555
Read address = 00001 data = 34
(2)
Load data F0 to address 5555
Pause 10 S
Read address = 7FFF2 Check DQ[3:0] of data outputs
(4)
Pause 10 S
(5) Normal Mode
Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7 - DQ0 (Hex); Address Format: A14 - A0 (Hex) (2) A1 - A18 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) The DQ[3:0] to indicate the sectors protect status as below: DQ0 0 64K Boot Block Unlocked by Software 64K Boot Block Locked by Software DQ1 16Kbytes Boot Block Unlocked by Software 16Kbytes Boot Block Locked by Software DQ2 64Kbytes Boot Block Unlocked by #TBL hardware trapping 64Kbytes Boot Block Locked by #TBL hardware trapping DQ3 Whole Chip Unlocked by #WP hardware trapping Except Boot Block Whole Chip Locked by #WP hardware trapping Except Boot Block
1
(5) The device returns to standard operation mode. (6) Optional 1-write cycle (write F0 (hex.) at XXXX address) can be used to exit the product identification/boot block lockout detection.
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Publication Release Date: December 19, 2002 Revision A2
W39V040FA
Boot Block Lockout Enable Acquisition Flow
Boot Block Lockout Feature Set Flow
Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 40/70 to address 5555 40 to lock 64K Boot Block 70 to lcok 16K Boot Block
Pause T BP
Exit
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W39V040FA
7. DC CHARACTERISTICS
Absolute Maximum Ratings
PARAMETER Power Supply Voltage to VSS Potential Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential Transient Voltage (<20 nS) on Any Pin to Ground Potential RATING -0.5 to +4.6 0 to +70 -65 to +150 -0.5 to VDD +0.5 -1.0 to VDD +0.5 UNIT V C C V V
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings May adversely affect the life and reliability of the device.
Programmer interface Mode DC Operating Characteristics
(VDD = 3.3V 0.3V, VSS = 0V, TA = 0 to 70 C)
PARAMETER Power Supply Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
SYM. ICC ILI ILO VIL VIH VOL VOH
TEST CONDITIONS In Read or Write mode, all DQs open Address inputs = 3.0V/0V, at f = 3 MHz VIN = VSS to VDD VOUT = VSS to VDD IOL = 2.1 mA IOH = -0.1mA
LIMITS MIN. TYP. -0.5 2.0 2.4 10 MAX. 20 90 90 0.8 VDD +0.5 0.45 -
UNIT mA
A A V V V V
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Publication Release Date: December 19, 2002 Revision A2
W39V040FA
FWH interface Mode DC Operating Characteristics
(VDD = 3.3V 0.3V, VSS= 0V, TA = 0 to 70 C)
PARAMETER Power Supply Current
SYM. ICC
TEST CONDITIONS All Iout = 0A, CLK = 33 MHz, in FWH mode operation. FWH4 = 0.9 VDD, CLK = 33 MHz, all inputs = 0.9 VDD / 0.1 VDD no internal operation FWH4 = 0.1 VDD, CLK = 33 MHz, all inputs = 0.9 VDD /0.1 VDD no internal operation. IOL = 1.5 mA IOH = -0.5 mA
LIMITS MIN. TYP. 12.5 MAX. 20
UNIT mA
Standby Current 1
Isb1
-
5
25
uA
Standby Current 2 Input Low Voltage Input Low Voltage of #INIT Input High Voltage Input High Voltage of #INIT Pin Output Low Voltage Output High Voltage
Isb2 VIL VILI VIH VIHI VOL VOH
-0.5 -0.5 0.5 VDD 1.35 V 0.9 VDD
3 -
10 0.3 VDD 0.2 VDD VDD +0.5 VDD +0.5 0.1 VDD -
mA
V V V V V V
Power-up Timing
PARAMETER Power-up to Read Operation Power-up to Write Operation SYMBOL TPU. READ TPU. WRITE TYPICAL 100 5 UNIT S mS
Capacitance
(VDD = 3.3V, TA = 25 C, f = 1 MHz)
PARAMETER I/O Pin Capacitance Input Capacitance
SYMBOL CI/O CIN
CONDITIONS VI/O = 0V VIN = 0V
MAX. 12 6
UNIT pF pF
- 16 -
W39V040FA
8. PROGRAMMER INTERFACE MODE AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load 0V to 0.9 VDD < 5 nS 1.5V/1.5V 1 TTL Gate and CL = 30 pF CONDITIONS
AC Test Load and Waveform
+3.3V
1.8K
DOUT
Input
30 pF (Including Jig and Scope) 0.9VDD 1.3K 0V Test Point 1.5V
Output
1.5V Test Point
- 17 -
Publication Release Date: December 19, 2002 Revision A2
W39V040FA
Programmer Interface Mode AC Characteristics, continued
Read Cycle Timing Parameters
(VDD = 3.3V 0.3V, VSS = 0V, TA = 0 to 70 C)
PARAMETER Read Cycle Time Row / Column Address Set Up Time Row / Column Address Hold Time Address Access Time Output Enable Access Time #OE Low to Active Output #OE High to High-Z Output Output Hold from Address Change
SYMBOL TRC TAS TAH TAA TOE TOLZ TOHZ TOH
W39V040FA MIN. 300 50 50 0 0 MAX. 150 75 35 -
UNIT nS nS nS nS nS nS nS nS
Write Cycle Timing Parameters
PARAMETER Reset Time Address Setup Time Address Hold Time R/#C to Write Enable High Time #WE Pulse Width #WE High Width Data Setup Time Data Hold Time #OE Hold Time Byte programming Time Sector/Page Erase Cycle Time Chip Erase Cycle Time SYMBOL TRST TAS TAH TCWH TWP TWPH TDS TDH TOEH TBP TPEC TEC MIN. 1 50 50 50 100 100 50 50 0 TYP. 35 20 75 MAX. 50 25 100 UNIT S nS nS nS nS nS nS nS nS S mS mS
Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is input high and (b) low level signal's reference level is input low. Ref. to the AC testing condition.
Data Polling and Toggle Bit Timing Parameters
PARAMETER #OE to Data Polling Output Delay #OE to Toggle Bit Output Delay SYMBOL TOEP TOET W39V040FA MIN. MAX. 40 40 nS nS UNIT
- 18 -
W39V040FA
9. TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE
Read Cycle Timing Diagram
#RESET TRST A[10:0] Column Address TAS R/ #C VIH #WE #OE TAA TOH TOE High-Z DQ[7:0] TOLZ Data Valid High-Z TOHZ TAH TRC Row Address TAS TAH Column Address Row Address
Write Cycle Timing Diagram
TRST #RESET
A[10:0]
Column Address TAS TAH
Row Address TAS TAH
R/ #C TCWH #OE TWP #WE TDS DQ[7:0] Data Valid TDH TWPH TOEH
- 19 -
Publication Release Date: December 19, 2002 Revision A2
W39V040FA
Timing Waveforms for Programmer Interface Mode, continued
Program Cycle Timing Diagram
Byte Program Cycle A[10:0] (Internal A[18:0]) DQ[7:0] 5555 AA 2AAA 55 5555 A0
Programmed Address
Data-In
R/ #C
#OE #WE TWP
TWPH
TBP
Byte 0
Byte 1
Byte 2
Byte 3
Internal Write Start
Note: The internal address A[18:0] are converted from external Column/Row address Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[18:11].
#DATA Polling Timing Diagram
A[10:0] (Internal A[18:0]) R/ #C An An An An
#WE
#OE TOEP DQ7 X X TBP or TEC X X
- 20 -
W39V040FA
Timing Waveforms for Programmer Interface Mode, continued
Toggle Bit Timing Diagram
A[10:0] R/ #C
#WE
#OE TOET DQ6 TBP or TEC
Boot Block Lockout Enable Timing Diagram
Six-byte code for Boot Block Lockout command A[10:0] (Internal A[18:0]) DQ[7:0] 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40/70
R/#C
#OE #WE
TWP TWPH SB0 SB1 SB2 SB3 SB4 SB5
TWC
Note: The internal address A[18:0] are converted from external Column/Row add Column/Row Address are mapped to the Low/High order internal addr i.e. Column Address A[10:0] are mapped to the internal A[10: Row Address A[7:0] are mapped to the internal A[18:11 When 40(hex) is loaded, the 64KByte are locked; while 70(hex) is loaded, the 16KByte is lo
- 21 -
Publication Release Date: December 19, 2002 Revision A2
W39V040FA
Timing Waveforms for Programmer Interface Mode, continued
Chip Erase Timing Diagram
Six-byte code for 3.3V-only software chip erase A[10:0] (Internal A[18:0]) DQ[7:0] 5555 AA 2AAA 5555 80 5555 2AAA 55 5555 10
55
AA
R/ #C
#OE TWP #WE SB0 TWPH SB1 SB2 SB3 SB4 SB5 Internal Erasure Starts TEC
Note: The internal address A[18:0] are converted from external Column/Row addre Column/Row Address are mapped to the Low/High order internal addre i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[18:11].
Sector/Page Erase Timing Diagram
Six-byte code for 3.3V-only Sector/Page Erase A[10:0] (Internal A[18:0]) DQ[7:0] 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA/PA 30/50
R/ #C
#OE #WE
TWP TWPH SB0 SB1 SB2 SB3 SB4 SB5
TPEC
Internal Erase starts
Note: The internal address A[18:0] are converted from external Column/Row address Column/Row Address are mapped to the Low/High order internal address i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[18:11]. SA = Sector Address and PA = Page Address, Please ref. to the "Table of Command Definition"
- 22 -
W39V040FA
10. FWH INTERFACE MODE AC CHARACTERISTICS
AC Test Conditions
PARAMETER Input Pulse Levels Input Rise/Fall Slew Rate Input/Output Timing Level Output Load 0.6 VDD to 0.2 VDD 1 V/nS 0.4VDD / 0.4VDD 1 TTL Gate and CL = 10 pF CONDITIONS
Read/Write Cycle Timing Parameters
(VDD = 3.3V 0.3V, VSS = 0V, TA = 0 to 70 C)
PARAMETER Clock Cycle Time Input Set Up Time Input Hold Time Clock to Data Valid
SYMBOL TCYC TSU THD TKQ
W39V040FA MIN. 30 7 0 2 MAX. 11
UNIT nS nS nS nS
Note: Minimum and Maximum time has different loads. Please refer to PCI specification.
Reset Timing Parameters
PARAMETER VDD stable to Reset Active Clock Stable to Reset Active Reset Pulse Width Reset Active to Output Float Reset Inactive to Input Active SYMBOL TPRST TKRST TRSTP TRSTF TRST MIN. 1 100 100 10 TYP. MAX. 50 UNIT mS S nS nS S
Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is input high and (b) low level signal's reference level is input low. Ref. to the AC testing condition.
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Publication Release Date: December 19, 2002 Revision A2
W39V040FA
11. TIMING WAVEFORMS FOR FWH INTERFACE MODE
Read Cycle Timing Diagram
TCYC
CLK
#RESET
TSU THD
FWH4 Start FWH Read FWH[3:0] Address XXXXb
XA[22]XXb XXA[18:16]
TSU THD
IDSEL M Size
TKQ TAR 1111b Sync Data D[3:0] D[7:4] TAR 1111b Tri-State Next Start
0000b
1101b 0000b
A[15:12] A[11:8]
A[7:4]
A[3:0]
0000 b]
Tri-State 0000b
1 Clock 1 Clock
Load Address in 7 Clocks
2 Clocks
1 Clock Data out 2 Clocks
2 Clocks
1 Clock
Note: When A22 = high, the host will read the BIOS code from the FWH d While A22 = low, the host will read the GPI (Add = FFBC0100 Product ID (Add = FFBC0000/FFBC0001) from the FWH dev
Write Cycle Timing Diagram
TCYC
CLK
#RESET
FWH4
Start FWH Write
TSU THD
IDSEL
Address XXXXb XXXXb
XXA[18:16]b A[15:12]
M Size
Data D[3:0] D[7:4]
TAR 1111b Tri-State
Sync 0000b 1 Clock
TAR 1111b
Next Start
FWH[3:0]
1110b 0000b
A[11:8]
A[7:4]
A[3:0]
0000b
Tri-State 0000b 1 Clock
1 Clock 1 Clock
Load Address in 7 Clocks
Load Data in 2 Clocks
2 Clocks
2 Clocks
- 24 -
W39V040FA
Timing Waveforms, for FWH Interface Mode, continued
Program Cycle Timing Diagram
CLK
#RESET
FWH4 Address
XXXXb XXXXb XXXXb X101b 0101b 0101b 0101b M Size 0000b 1010b
1st Start FWH[3:0 ] 1110b
IDSEL
Data
1010b
TAR 1111b Tri-State
Sync 0000b 1 Clock
TAR 1111b Tri-State
Start next command
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
2 Clocks
1 Clock
Write the 1st command to the device in FWH mode.
CLK
#RESET
FWH4 Address
XXXXb XXXXb XXXXb X010b 1010b 1010b 1010b
2nd Start FWH[3:0 ] 1110b
IDSEL
M Size 0000b 0101b
Data
0101b
TAR 1111b Tri-State
Sync 0000b 1 Clock
TAR 1111b Tri-State
Start next command
0000b
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
Load Data "55" in 2 Clocks
2 Clocks
2 Clocks
1 Clock
Write the 2nd command to the device in FWH mode.
CLK
#RESET
FWH4 Data
0000b 1010b
3rd Start FWH[3:0 ] 1110b
IDSEL
Address
XXXXb XXXXb XXXXb X101b 0101b 0101b 0101b
M Size 0000b
TAR 1111b Tri-State
Sync 0000b 1 Clock
TAR 1111b Tri-State
Start next command
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "A0" in 2 Clocks
2 Clocks
2 Clocks
1 Clock
Write the 3rd command to the device in FWH mode.
CLK
#RESET
FWH4
IDSEL
Internal program start 4th Start Address
XXXXb XXXXb
XA[18:16]b
M Size A[11:8] A[7:4] A[3:0] 0000b D[3:0]
Data
D[7:4]
TAR 1111b Tri-State
Sync 0000b 1 Clock
TAR 1111b Tri-State Internal program start
FWH[3:0 ]
1110b
0000b
A[15:12]
1 Clock 1 Clock
Load Ain in 7 Clocks
Load Din in 2 Clocks
2 Clocks
2 Clocks
Write the 4th command(target location to be programmed) to the device in FWH mode.
- 25 -
Publication Release Date: December 19, 2002 Revision A2
W39V040FA
Timing Waveforms for FWH Interface Mode, continued
#DATA Polling Timing Diagram
CLK
#RESET
FWH4 Start FWH[3:0] 1110b IDSEL 0000b
XXXXb XXXXb
XXA[18:16]b
Address
An[15:12] An[11:8] An[7:4] An[3:0]
M Size
Data Dn[3:0] Dn[7:4] 1111b
TAR Tri-State
Sync 0000b
TAR 1111b Tri-State
Next Start
0000b
1 Clock 1 Clock
Load Address "An" in 7 Clocks
Load Data "Dn" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the last command(program or erase) to the device in FWH mode.
CLK
#RESET XXXXb FWH4 Start FWH[3:0] 1101b IDSEL 0000b
XXXXb XXXXb
XXA[18:16]b
Address
An[15:12] An[11:8] An[7:4] An[3:0]
M Size
TAR 1111b Tri-State
Sync 0000b
Data XXXXb Dn7,xxx
TAR 1111b Tri-State
Next Start
0000b
1 Clock 1 Clock
Load Address in 7 Clocks
2 Clocks
1 Clock Data out 2 Clocks
2 Clocks
1 Clock
Read the DQ7 to see if the internal write complete or not.
CLK
#RESET
FWH4 Start FWH[3:0] 1101b IDSEL 0000b
XXXXb XXXXb
XXA[18:16]b
Address
An[15:12] An[11:8] An[7:4] An[3:0]
M Size
TAR 1111b Tri-State
Sync 0000b
Data XXXXb Dn7,xxx
TAR 1111b Tri-State
Next Start
0000b
1 Clock 1 Clock
Load Address in 7 Clocks
2 Clocks
1 Clock Data out 2 Clocks
2 Clocks
1 Clock
When internal write complete, the DQ7 will equal to Dn7.
- 26 -
W39V040FA
Timing Waveforms for FWH Interface Mode, continued
Toggle Bit Timing Diagram
CLK
#RESET
FWH4 Start FWH[3:0] 1110b IDSEL 0000b
XXXXb XXXXb
XXA[18:16]b
Address
A[15:12] A[11:8] A[7:4] A[3:0]
M Size
Data D[3:0] D[7:4] 1111b
TAR Tri-State
Sync 0000b
TAR 1111b Tri-State
Next Start
0000b
1 Clock 1 Clock
Load Address "An" in 7 Clocks
Load Data "Dn" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the last command(program or erase) to the device in FWH mode.
CLK
#RESET
FWH4 Start FWH[3:0] 1101b IDSEL 0000b
XXXXb XXXXb XXXXb
Address XXXXb XXXXb XXXXb XXXXb
M Size
TAR 1111b Tri-State
Sync 0000b
Data XXXXb
X,D6,XXb
TAR 1111b Tri-State
Next Start
0000b
1 Clock 1 Clock
Load Address in 7 Clocks
2 Clocks
1 Clock Data out 2 Clocks
2 Clocks
1 Clock
Read the DQ6 to see if the internal write complete or not.
CLK
#RESET
FWH4 Start FWH[3:0] 1101b Address
XXXXb XXXXb XXXXb
IDSEL 0000b
M Size
TAR 1111b Tri-State
Sync 0000b
Data XXXXb
X,D6,XXb
TAR 1111b Tri-State
Next Start
XXXXb
XXXXb
XXXXb
XXXXb
0000b
1 Clock 1 Clock
Load Address in 7 Clocks
2 Clocks
1 Clock
Data out 2 Clocks
2 Clocks
1 Clock
When internal write complete, the DQ6 will stop toggle.
- 27 -
Publication Release Date: December 19, 2002 Revision A2
W39V040FA
Timing Waveforms for FWH Interface Mode, continued
Boot Block Lockout Enable Timing Diagram
CLK
#RESET FWH4 IDSEL 0000b
XXXXb XXXXb XXXXb
1st Start FWH[3:0] 1110b
Address X101b 0101b 0101b 0101b
M Size
Data 1010b 1010b 1111b
TAR Tri-State
Sync 0000b
TAR 1111b Tri-State
Start next command
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 1st command to the device in FWH mode.
CLK #RESET FWH4 Address
XXXXb XXXXb XXXXb
2nd Start IDSEL FWH[3:0] 1110b 0000b
M Size
Data 0101b 0101b 1111b
TAR Tri-State
Sync 0000b
TAR 1111b Tri-State
Start next command
X010b
1010b
1010b
1010b
0000b
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clocks
2 Clocks
1 Clock
Write the 2nd command to the device in FWH mode.
CLK #RESET FWH4 IDSEL 0000b
XXXXb XXXXb XXXXb
3rd Start FWH[3:0] 1110b
Address X101b 0101b 0101b 0101b
M Size
Data 0000b 1000b
TAR 1111b Tri-State
Sync 0000b
TAR 1111b Tri-State
Start next command
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "80" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 3rd command to the device in FWH mode.
CLK
#RESET FWH4 IDSEL 0000b
XXXXb XXXXb XXXXb
4th Start FWH[3:0] 1110b
Address X101b 0101b 0101b 0101b
M Size
Data 1010b 1010b 1111b
TAR Tri-State
Sync 0000b
TAR 1111b Tri-State
Start next command
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 4th command to the device in FWH mode.
CLK #RESET FWH4 Address
XXXXb XXXXb XXXXb
5th Start FWH[3:0] 1110b
IDSEL 0000b
M Size
Data 0101b 0101b
TAR 1111b Tri-State
Sync 0000b
TAR 1111b Tri-State
Start next command
X010b
1010b
1010b
1010b
0000b
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 5th command to the device in FWH mode.
CLK #RESET FWH4 6th Start FWH[3:0] 1110b IDSEL 0000b
XXXXb XXXXb XXXXb
Address X101b 0101b 0101b 0101b
M Size
Data 0000b 0100b/ 0111b
TAR 1111b Tri-State
Sync 0000b
TAR 1111b Tri-State
Start next command
0000b
1 Clock 1 Clock
Load Address "5555" 7 Clocks
Load Data "40" or "70" in Two Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 6th command to the device in FWH mode.
- 28 -
W39V040FA
Timing Waveforms for FWH Interface Mode, continued
Chip Erase Timing Diagram
CLK
#RESET
FWH4 IDSEL 0000b
XXXXb XXXXb XXXXb
1st Start FWH[3:0] 1110b
Address X101b 0101b 0101b 0101b
M Size
Data 1010b 1010b 1111b
TAR Tri-State
Sync 0000b 1111b
TAR Tri-State
Start next command
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 1st command to the device in FWH mode.
CLK
#RESET
FWH4 Address
XXXXb XXXXb XXXXb M Size
2th Start FWH[3:0] 1110b
IDSEL 0000b
Data 0101b 0101b 1111b
TAR Tri-State
Sync 0000b 1111b
TAR Tri-State
Start next command
X010b
1010b
1010b
1010b
0000b
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 2nd command to the device in FWH mode.
CLK
#RESET
FWH4 Data 0000b 1000b TAR 1111b Tri-State Sync 0000b 1111b TAR Tri-State Start next command
3th Start FWH[3:0] 1110b
IDSEL 0000b
XXXXb XXXXb XXXXb
Address X101b 0101b 0101b 0101b
M Size
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "80" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 3rd command to the device in FWH mode.
CLK
#RESET
FWH4
FWH[3:0]
4th Start 1110b
IDSEL 0000b
XXXXb XXXXb XXXXb
Address X101b 0101b 0101b 0101b
M Size
Data 1010b 1010b 1111b
TAR Tri-State
Sync 0000b 1111b
TAR Tri-State
Start next command
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 4th command to the device in FWH mode.
CLK
#RESET
FWH4 Start next command
5th Start FWH[3:0] 1110b
IDSEL 0000b
XXXXb XXXXb XXXXb
Address X010b 1010b 1010b 1010b
M Size
Data 0101b 0101b
TAR 1111b Tri-State
Sync 0000b 1111b
TAR Tri-State
0000b
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 5th command to the device in FWH mode.
CLK
#RESET
FWH4
Internal erase start 6th Start IDSEL 0000b
XXXXb XXXXb XXXXb
Address X101b 0101b 0101b 0101b
M Size
Data 0000b 0001b
TAR 1111b Tri-State
Sync 0000b 1111b
TAR Tri-State Internal erase start
FWH[3:0]
1110b
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "10" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
Write the 6th command to the device in FWH mode.
- 29 -
Publication Release Date: December 19, 2002 Revision A2
W39V040FA
Timing Waveforms for FWH Interface Mode, continued
Sector Erase Timing Diagram
CLK
#RESET
FWH4 Address
XXXXb XXXXb XXXXb
1st Start FWH[3:0] 1110b
IDSEL 0000b
M Size
Data 1010b 1010b 1111b
TAR Tri-State
Sync 0000b 1111b
TAR Tri-State
Start next command
X101b
0101b
0101b
0101b
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 1st command to the device in FWH mode.
CLK
#RESET
FWH4 Address
XXXXb XXXXb XXXXb
2nd Start IDSEL FWH[3:0] 1110b 0000b
M Size
Data 0101b 0101b 1111b
TAR Tri-State
Sync 0000b 1111b
TAR Tri-State
Start next command
X010b
1010b
1010b
1010b
0000b
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 2nd command to the device in FWH mode.
CLK
#RESET
FWH4
M Size
3rd Start IDSEL FWH[3:0] 1110b 0000b
XXXXb XXXXb XXXXb
Address X101b 0101b 0101b 0101b
Data 0000b 1000b
TAR 1111b Tri-State
Sync 0000b
TAR 1111b Tri-State
Start next command
0000b
1 Clocks1 Clocks
Load Address "5555" in 7 Clocks
Load Data "80" in 2 Clocks
2 Clocks
1 Clocks
2 Clocks
1 Clocks
Write the 3rd command to the device in FWH mode.
CLK
#RESET
FWH4
FWH[3:0]
4th Start 1110b
IDSEL 0000b
XXXXb XXXXb XXXXb
Address X101b 0101b 0101b 0101b
M Size
Data 1010b 1010b
TAR 1111b Tri-State
Sync 0000b
TAR 1111b Tri-State
Start next command
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 4th command to the device in FWH mode.
CLK
#RESET
FWH4 Start next command Tri-State
5th Start IDSEL FWH[3:0] 1110b 0000b
XXXXb XXXXb XXXXb
Address X010b 1010b 1010b 1010b
M Size
Data 0101b 0101b
TAR 1111b Tri-State
Sync 0000b
TAR 1111b
0000b
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 5th command to the device in FWH mode.
CLK
#RESET
FWH4
Internal erase start 6th Start IDSEL 0000b
XXXXb XXXXb
XA[18:16]b
Address XXXXb XXXXb XXXXb XXXXb
M Size
Data 0000b 0011b
TAR 1111b Tri-State
Sync 0000b
TAR 1111b Tri-State Internal erase start
FWH[3:0] 1110b
0000b
1 Clock 1 Clock
Load Sector Address in 7 Clocks
Load Din in 2 Clocks
2 Clocks
1 Clock
2 Clocks
Write the 6th command(target sector to be erased) to the device in FWH mode.
- 30 -
W39V040FA
Timing Waveforms for FWH Interface Mode, continued
Page Erase Timing Diagram
CLK #RESET FWH4 Address
XXXXb XXXXb XXXXb
1st Start FWH[3:0] 1110b
IDSEL 0000b
M Size
Data 1010b 1010b 1111b
TAR Tri-State
Sync 0000b 1111b
TAR Tri-State
Start next command
X101b
0101b
0101b
0101b
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 1st command to the device in FWH mode.
CLK
#RESET
FWH4 Address
XXXXb XXXXb XXXXb
2nd Start IDSEL FWH[3:0] 1110b 0000b
M Size
Data 0101b 0101b 1111b
TAR Tri-State
Sync 0000b 1111b
TAR Tri-State
Start next command
X010b
1010b
1010b
1010b
0000b
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 2nd command to the device in FWH mode.
CLK
#RESET FWH4
M Size
3rd Start IDSEL FWH[3:0] 1110b 0000b
XXXXb XXXXb XXXXb
Address X101b 0101b 0101b 0101b
Data 0000b 1000b
TAR 1111b Tri-State
Sync 0000b
TAR 1111b Tri-State
Start next command
0000b
1 Clocks1 Clocks
Load Address "5555" in 7 Clocks
Load Data "80" in 2 Clocks
2 Clocks
1 Clocks
2 Clocks
1 Clocks
Write the 3rd command to the device in FWH mode.
CLK
#RESET FWH4
FWH[3:0]
4th Start 1110b
IDSEL 0000b
XXXXb XXXXb XXXXb
Address X101b 0101b 0101b 0101b
M Size
Data 1010b 1010b
TAR 1111b Tri-State
Sync 0000b
TAR 1111b Tri-State
Start next command
0000b
1 Clock 1 Clock
Load Address "5555" in 7 Clocks
Load Data "AA" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 4th command to the device in FWH mode.
CLK
#RESET FWH4 Start next command Tri-State
5th Start IDSEL FWH[3:0] 1110b 0000b
XXXXb XXXXb XXXXb
Address X010b 1010b 1010b 1010b
M Size
Data 0101b 0101b
TAR 1111b Tri-State
Sync 0000b
TAR 1111b
0000b
1 Clock 1 Clock
Load Address "2AAA" in 7 Clocks
Load Data "55" in 2 Clocks
2 Clocks
1 Clock
2 Clocks
1 Clock
Write the 5th command to the device in FWH mode.
CLK
#RESET FWH4 Internal erase start 6th Start FWH[3:0] 1110b 0000b
XXXXb XXXXb
XA[18:16]b
IDSEL
Address
A[15:12]
M Size
Data 0000b 0101b
TAR 1111b Tri-State
Sync 0000b
TAR 1111b Tri-State Internal erase start
XXXXb
XXXXb
XXXXb
0000b
1 Clock 1 Clock
Load Page Address in 7 Clocks
Load Din in 2 Clocks
2 Clocks
1 Clock
2 Clocks
Write the 6th command(target page to be erased) to the device in FWH mode.
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Publication Release Date: December 19, 2002 Revision A2
W39V040FA
Timing Waveforms for FWH Interface Mode, continued
FGPI Register/Product ID Readout Timing Diagram
CLK #RESET
FWH4
Start FWH[3:0] 1101b
IDSEL 0000b A[27:24] A[23:20] A[19:16]
Address 0000b 0001b /0000b 0000b 0000b /0001b
M Size
TAR Tri-State 1111b
Sync 0000b D[3:0]
Data D[7:4]
TAR Tri-State 1111b
Next Sta
0000b
1 Clock 1 Clock
Load Address "FFBC0100(hex)" in 7 Clocks for GPI Register & "FFBC0000(hex)/FFBC0001(hex) for Product ID
2 Clocks
1 Clock Data out 2 Clocks
2 Clocks
1 Clock
Note: During the GPI read out mode, the DQ[4:0] will capture the states(High or Low) of the FGPI[4:0] input pins. The DQ[7:5] are reserved pins
Reset Timing Diagram
VDD
TPRST
CLK TKRST TRSTP TRST
#RESET TRST
F
FWH[3:0]
FWH4
- 32 -
W39V040FA
12. ORDERING INFORMATION
PART NO. W39V040FAP W39V040FAQ W39V040FAT
Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
ACCESS TIME (nS) 11 11 11
POWER SUPPLY CURRENT MAX. (mA) 20 20 20
STANDBY VDD CURRENT MAX. (mA) 10 10 10
PACKAGE 32L PLCC 32L STSOP 40L TSOP
13. HOW TO READ THE TOP MARKING
Example: The top marking of 32-pin STSOP W39V040FAQ
W39V040FAQ 2138977A-A12 149OBSA
1st line: Winbond logo 2nd line: the part number: W39V040FAQ 3rd line: the lot number 4th line: the tracking code: 149 O B SA 149: Packages made in '01, week 49 O: Assembly house ID: A means ASE, O means OSE, ...etc. B: IC revision; A means version A, B means version B, ...etc. SA: Process code
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Publication Release Date: December 19, 2002 Revision A2
W39V040FA
14. PACKAGE DIMENSIONS
32L PLCC
Symbol
HE E
Dimension in Inches
Dimension in mm
Min. Nom. Max.
0.140 0.020 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075 0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090 0.115 0.032 0.022 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.004 0 10
Min. Nom. Max.
3.56 0.50 2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91 2.80 0.71 0.46 0.25 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29 2.93 0.81 0.56 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.10 0 10
4
1
32
30
5
29
GD D HD
13
21
A A1 A2 b1 b c D E e GD GE HD HE L y Notes:
14
20
c
L A2 A
1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusio 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection sepc.
Seating Plane
e
b b1 GE
A1 y
32L STSOP
HD D c
Symbol Dimension in Inches Dimension in mm Min. Nom. Max. Min. Nom. Max.
1.20 0.05 0.95 0.17 0.10 1.00 0.22 ----12.40 8.00 14.00 0.50 0.028 0.50 0.60 0.80 0.004 3 5 0.00 0 3 0.10 5 0.70 0.15 1.05 0.27 0.21
e
E A A1 A2 b c D E HD e L L1 Y
0.047 0.002 0.035 0.007 0.004 0.040 0.009 ----0.488 0.315 0.551 0.020 0.020 0.000 0 0.024 0.031 0.006 0.041 0.010 0.008
b
L L1
A1 A2 A
Y
- 34 -
W39V040FA
Package Dimensions, continued
40L TSOP (10 mm x 20 mm)
R R 0.08 0.02 0.003 0.008
- 35 -
Publication Release Date: December 19, 2002 Revision A2
W39V040FA
15. VERSION HISTORY
VERSION A1 A2 DATE June 19, 2002 Dec. 19, 2002 PAGE 23 Initial Issued Delete AC Test Load and Waveform. Add a note below Read/Write Cycle Timing Parameter 15 Modify PGM mode power supply current (Icc) parameter from 20 mA (typ.) to 10 mA (typ.) and 30 mA (max.) to 20 mA (max.) Modify FWH mode power supply current (Icc) parameter from 40 mA (typ.) to 12.5 mA (typ.) and 60 mA (max.) to 20 mA (max.) Modify Standby current (Isb1) parameter from 20 A (typ.) to 5 A (typ.) and 100 A (max.) to 25 A (max.) DESCRIPTION
1, 16, 33
16
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 36 -

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